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acpl-m21l, acpl-021l and acpl-024l low power, 5 mbd digital cmos optocoupler data sheet a 0.1 f bypass capacitor must be connected between pins vdd and gnd truth table (positive logic) led vo on high off low features ? cmos output ? wide supply voltage: 2.7 v C 5.5 v ? low power supply current i dd : 1.1 ma/channel max. ? low forward current i f : 1.6 ma min ? speed: 5 mbd typ ? pulse width distortion (pwd): 200 ns max ? propagation delay skew (tpsk): 220 ns max ? propagation delay (tp): 250 ns max ? common mode rejection: 25 kv/ s min at v cm = 1000 v ? hysteresis: 0.2 ma typ ? temperature range: -40 c to 105 c ? safety and regulatory approvals C ul 1577 recognized C 3750 vrms for 1 minute for acpl-m21l/021l/024l C csa approval C iec/en 60747-5-5, approval for reinforced insulation applications ? low isolation of high speed logic systems ? computer peripheral interface ? microprocessor system interface ? ground loop elimination ? pulse transformer replacement ? high speed line receiver ? power control systems description acpl-m21l (single channel so-5 package), acpl-021l (single channel so-8 package) and acpl-024l (dual channel so-8 package) are optically-coupled logic gates. the detector ic has cmos output stage and optical receiver input stage with built-in schmitt trigger to provide logic-compatible waveforms, eliminating the need for additional waveshaping. an internal shield on the acpl-m21l/021l/024l guar - antees common mode transient immunity of 25 kv/s at a common mode voltage of 1000 v. the acpl-x2xl optocouplers' series operates from a 2.7 v to 5.5 v supply with guaranteed ac and dc performance from an extended temperature range of -40 c to 105 c. glitches free output upon power-up and power-down of optocou - pler. functional diagram acpl-021l 6 4 anode vdd gnd vo shield 1 3 5 cathode 2 3 8 5 6 anode vdd gnd vo shield 1 nc nc 4 7 cathode nc acpl-m21l acpl-024l 4 1 v dd v 01 anode1 cathode1 v 02 gnd cathode2 anode2 shield 3 2 5 8 6 7 lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
2 ordering information acpl-m21l, acpl-024l and acpl-021l are ul recognized with 3750 v rms for 1 minute per ul1577. part number option package surface mount tape & reel ul1577 5000 v rms / 1 minute rating iec/en 60747-5-5 quantity rohs compliant acpl-m21l -000e so-5 x 100 per tube -060e x x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel acpl-024l -000e so-8 x 100 per tube -060e x x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel acpl-021l -000e so-8 x 100 per tube -060e x x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: ACPL-M21L-500E to order product of so-5 package in tape and reel packaging with rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 package outline drawings acpl-m21l so-5 package mxxx xxx 7.0 0.2 (0.276 0.008) 2.5 0.1 (0.098 0.004) 0.102 0.102 (0.004 0.004) 4.4 0.1 (0.173 0.004) 1.27 (0.050) bsc 0.15 0.025 (0.006 0.001) 0.71 (0.028) min 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) dimensions in millimeters (inches). note: foating lead protrusion is 0.15 mm (6 mils) max. * maximum mold ash on each side is 0.15 mm (0.006). 7 max. max. lead coplanarity = 0.102 (0.004) 8.27 (0.325) 1.8 (0.072) 2.5 (0.10) 1.3 (0.05) 0.5 (0.02) 4.4 (0.17) land pattern recommendation 0.3 (0.01)
4 acpl-024l/021l so-8 package solder refow profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. regulatory information the acpl-m21l/024l/021l is approved by the following organizations: ul approval under ul 1577, component recognition program up to v iso = 3750 v rms for acpl-m21l/024l/021l csa approval under csa component acceptance notice #5. iec/en 60747-5-5 (option 060 only) xxxv yww 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * total package length (inclusive of mold ash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). note: floating lead protrusion is 0.15 mm (6 mils) max. lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. land pattern recommendation 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) 3.95 (0.156) 1.3 (0.5)
5 insulation and safety related specifcations parameter symbol acpl-m21l acpl-024l acpl-021l units conditions minimum external air gap (clearance) l(101) 5 4.9 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 5 4.8 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti 175 175 volts din iec 112/vde 0303 part 1 isolation group iiia iiia material group (din vde 0110, 1/89, table 1) iec/en 60747-5-5 insulation characteristics* (option 060) description symbol characteristic unit acpl-m21l/ 024l/021l installation classifcation per din vde 0110/39, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 600 v rms for rated mains voltage 1000 v rms i C iv i C iii i C ii climatic classifcation 55/105/21 pollution degree (din vde 0110/39) 2 maximum working insulation voltage v iorm 567 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1063 v peak input to output test voltage, method a* v iorm x 1.6 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 896 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 6000 v peak safety-limiting values C maximum values allowed in the event of a failure. case temperature t s 150 c input current** i s, input 150 ma output power** p s, output 600 mw insulation resistance at ts, v io = 500 v r s >10 9 w * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (iec/en 60747-5-5) for a detailed description of method a and method b partial discharge test profles. ** refer to the following fgure for dependence of p s and i s on ambient temperature.
6 absolute maximum ratings parameter symbol min max units condition storage temperature t s -55 125 c operating temperature t a -40 105 c reverse input voltage v r 5 v supply voltage v dd 6.5 v average forward input current i f 8 ma peak forward input current i f(tran) 1 a 1 s pulse width, < 300 pulses per second output current i o 10 ma at max v dd output voltage v o -0.5 v dd +0.5 v lead solder temperature t ls 260 c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see package outline drawings section recommended operating conditions parameter symbol min max units operating temperature t a -40 105 c input current, low level i fl 0 250 a input current, high level i fh 1.6* 6 ma power supply voltage v dd 2.7 5.5 v forward input voltage v f (off) 0.8 v * the initial switching threshold is 1.6 ma or less. it is recommended that 2.2 ma be used to permit at least a 20% led degradation guardband. electrical specifcations (dc) over recommended temperature (t a = -40 c to 105 c) and supply voltage (2.7 v v dd 5.5 v). all typical specifcations are at v dd = 2.7 v, t a = 25 c, unless otherwise specifed. parameter symbol channel min typ max units test conditions input forward voltage v f 1.5 2.0 v i f = 2.2 ma (figure 1 & 2) input reverse breakdown voltage bv r 8 11 v i r = 10 a logic high output voltage v oh v dd - 0.1 v i f = 2.2 ma, i o = -20 a v dd - 1.0 v i f = 2.2 ma, i o = -3.2 ma (figure 3) logic low output voltage v ol 0.001 0.1 v i f = 0 ma, i o = 20 a 0.15 0.4 v i f = 0 ma, i o = 3.2 ma (figure 4) input threshold current i th 0.5 1.4 ma figure 5 logic low output supply current i ddl single 0.6 1.1 ma v f = 0 v, v dd = 5.5 v, i o = open (figure 6) dual 1.2 2.2 logic high output supply current i ddh single 0.5 1.1 ma i f = 2.2 ma, v dd = 5.5 v, i o = open (figure 7) dual 1.0 2.2 input capacitance c in 77 pf f = 1 mhz, v f = 0 v input diode temperature coefcient v f / t a -1.9 mv/ c i f = 2.2 ma
7 switching specifcations (ac) over recommended temperature (t a = -40 c to +105 c), supply voltage (2.7 v v dd 5.5 v). all typical specifcations are at v dd = 2.7 v, t a = 25 c parameter symbol min typ max units test conditions propagation delay time to logic low output [1] t phl 130 250 ns i f =2.2ma, c l =15pf (figure 8, 12) cmos signal levels propagation delay time to logic high output [1] t plh 115 250 ns i f =2.2ma, c l =15pf (figure 9, 12) cmos signal levels pulse width distortion [2] pwd 200 ns cmos signal levels propagation delay skew [3] t psk 220 ns output rise time (10% C 90%) t r 11 ns i f = 2.2 ma, c l = 15 pf, cmos signal levels. output fall time (90% C 10%) t f 11 ns i f = 2.2 ma, c l = 15 pf, cmos signal levels. static common mode transient immunity at logic high output [4] |cm h | 25 40 kv/ s v cm = 1000 v, t a = 25 c, i f = 2.2 ma, c l = 15 pf, v i = 5 v (r t = 1.6 k w ) or v i = 3.3 v (r t = 840 w ) cmos signal levels figure 13 static common mode transient immunity at logic low output [5] |cm l | 25 40 kv/ s v cm = 1000 v, t a = 25 c, i f = 0 ma, c l = 15 pf, v i = 0 v (r t = 1.6 k w ) or (r t = 840 w ) cmos signal levels figure 13 notes: 1. t phl propagation delay is measured from the 50% (v in or i f ) on the falling edge of the input pulse to the 50% v dd of the falling edge of the v o signal. t plh propagation delay is measured from the 50% (v in or i f ) on the rising edge of the input pulse to the 50% level of the rising edge of the v o signal 2. pwd is defned as |t phl - t plh | 3. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 4. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. cm l is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state. 6. use of a 0.1 f bypass capacitor connected between vdd and ground is recommended. package characteristics all typical at t a = 25 c parameter symbol part number min typ max units test conditions input-output insulation v iso acpl-m21l/ 024l/021l 3750 v rms rh < 50% for 1 min. t a = 25 c input-output resistance r i-o 10 12 w v i-o = 500 v input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25 c
8 figure 1. forward voltage vs. temperature figure 2. forward current vs forward voltage figure 3. logic high output voltage vs supply voltage figure 4. logic low output voltage vs. temperature figure 5. input threshold current vs. temperature figure 6. logic low output supply current vs. temperature 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -40 -20 0 20 40 60 80 100 v f - forward voltage - v t a - temperature - c 0.01 0.1 1 10 100 1.3 1.4 1.5 1.6 1.7 1.8 i f - forward current - ma v f - forward voltage - v 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 v oh - high level output voltage - v v dd - supply voltage - v 0 0.05 0.1 0.15 0.2 0.25 -40 -20 0 20 40 60 80 100 v ol - low level output voltage - v t a - temperature - c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -40 -20 0 20 40 60 80 100 i th - input threshold current - ma t a - temperature - c i th _3.3 v i th _5.0 v i o = -3.2 ma i ddl @ 3.3 v i ddl @ 5.0 v v dd = 3.3 v v f = 0 v i o = 3.2 ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -40 -20 0 20 40 60 80 100 i ddl - logic low output supply current - ma t a - temperature - c
9 figure 7. logic high output supply current vs. temperature figure 8. propagation delay, t phl vs. temperature figure 9. propagation delay, t plh vs. temperature figure 11. output voltage vs input current @ vdd = 5 v figure 10. output voltage vs input current @ vdd = 3.3 v v dd = 3.3 v v dd = 5.0 v v dd = 2.7 v i ddh_ 3.3 v i ddh_ 5.0 v v dd = 2.7 v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i ddh - logic high output supply current - ma -40 -20 0 20 40 60 80 100 t a - temperature - c t a - temperature - c t a - temperature - c -40 -20 0 20 40 60 80 100 50 60 70 80 90 100 110 120 130 140 150 t p - propagation delay - ns i f = 1.6, 2.2 and 6 ma 50 60 70 80 90 100 110 120 130 140 150 t plh - propagation delay - ns -40 -20 0 20 40 60 80 100 i f = 1.6 ma i f = 2.2 ma i f = 6.0 ma 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 vo - output voltage - v i f - input current - a i f - input current - a 0 1 2 3 4 5 6 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 v o - o u t p u t v o l t a g e - v
10 figure 12. circuit for t plh , t phl , t r , t f * 0.1 f bypass ? see note 6 above. [6] pulse gen t r = t f = 11 ns f = 1.0 mhz 50% duty cycle vdd * output v o monitoring node rm input monitoring node c l = 15 pf i f pulse gen t r = t f = 11 ns f = 1.0 mhz 50% duty cycle vdd output v o monitoring node rm input monitoring node c l = 15 pf i f pulse gen t r = t f = 11 ns f = 1.0 mhz 50% duty cycle * vdd output v o monitoring node rm input monitoring node c l = 15 pf i f acpl-m21l acpl-021l acpl-024l input i f output v o i f (on) 0 ma 50% i f (on) v oh v ol 50% t plh t phl 6 4 shield 1 3 5 4 1 shield 3 2 5 8 6 7 2 3 8 5 6 shield 1 4 7
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-3462en - april 15, 2013 figure 13. recommended printed circuit board layout and input current limiting resistor selection acpl-m21l, acpl-021l, acpl-024l: v i = 3.3 v: r 1 = 510 w 1%, r 2 = 330 w 1% v i = 5.0 v: r 1 = 1 k w 1%, r 2 = 600 w 1% r t = r 1 + r 2 r 1 /r 2 1.5 5 4 6 3 1 xxx yww i f gnd 1 v o v dd c gnd 2 v i r 1 r 2 acpl-m21l acpl-021l 5 3 4 2 7 6 8 1 xxx yww i f v o1 v dd c gnd 2 v i r 1 gnd 2 r 2 v o2 acpl-024l 5 3 4 2 7 6 8 1 xxx yww i f gnd 1 v o1 v dd c gnd 2 v i r 1 r 2 i f gnd 2 v i r 1 r 2 v o2 c = 0.1f

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